COURSE DESCRIPTION

This course provides an in-depth introduction to RTL (Register Transfer Level) design with Verilog, one of the industry’s most used hardware description languages. Participants will learn how to design, simulate, and synthesise digital circuits using Xilinx Vivado, a potent FPGA design suite, through hands-on experience. Students who successfully complete this course will have the knowledge and abilities necessary to work on real-world digital design projects, optimise designs for the use of power and resources, and handle constraints and timing.

OBJECTIVES

1. Learn the Verilog Language: Become well-versed in the syntax, semantics, and uses of Verilog in digital design.
2. Study Design Methodologies: Investigate and comprehend the implications of various digital design abstraction levels.
3. Practical Utilisation of Xilinx Vivado: Gain experience using Xilinx Vivado for design, simulation, synthesis, and verification in a real-world setting.
4. Design and Analyse Digital Circuits: Learn how to create, simulate, and optimise combinational and sequential digital circuits..
5. Optimise Power and Performance: In digital designs, use strategies for resource allocation and power optimisation.
6. Handle Timing limitations: To ensure the reliable operation of digital circuits, understand and apply timing constraints.

CERTIFICATION

Certification will be provided by TULSI TECH.

LEARNING OUTCOMES

Students will be capable of the following by the end of this course:

Verilog Proficiency: The ability to write and understand Verilog code for digital circuit design.
Module Design: Create and maintain Verilog modules with the proper port declarations and parameterization.
Abstract Modelling: Make use of Verilog’s gate-level, data flow, and behavioural modelling tools.
Simulation and Synthesis: To verify and execute digital designs, carry out simulation and synthesis using Xilinx Vivado.
Digital Circuit Design: Construct and evaluate circuits using combinational and sequential logic.
Design optimisation: Use methods to maximise FPGA resource and power consumption.
Timing Study: To guarantee design dependability, carry out timing analysis and apply limitations.

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